MOGON2 Hybrid Memory

Abstract

The ever-increasing demand of HPC applications for more computational power and higher memory capacities as well as these scalability issues force manufacturers and the HPC community to pursue alternative architectures beyond DRAM. \emph{Non-volatile main memory} (NVMM) is an umbrella term covering a number of upcoming memory technologies which do not need constant cell refreshing to sustain their voltage levels. They enable significant reductions of the static energy consumption and also can be manufactured in denser chips. NVMMs are therefore expected to have lower costs than DRAM. Most NVMM technologies can only endure a limited number of writes and have an asymmetric read/write performance. They therefore cannot simply replace DRAM as main memory.

DRAM-NVMM architectures are shown to be effective in reducing the power consumption and costs with minimal performance impact. Such architectures, however, are mostly not designed for HPC environments and cannot, due to their complex algorithms, be employed without significant hardware modifications. The few previously proposed DRAM-NVMM architectures for HPC operate by first profiling complete application runs and then statically decide the data placement for future runs. This approach is not portable and can only be used in few predefined scenarios.

The goal of this project is to take advantage of NVMMs promising characteristics in HPC and to mitigate their shortcomings, by employing both DRAM and NVMMs as main memory. The hybrid memory should simultaneously consider NVMM characteristics, online profiling without the need for a prior analysis, and the applicability to HPC programs without source code modifications. The overhead should be minimized, while the effect of replacing DRAM with NVMM also should not be noticeable to HPC users.