TUK TUK-OHA2

Optimization of Hardware Architectures

Abstract

To build modern, efficient hardware architectures for specific applications, various trade-offs between different performance indicators and implementation efficiency have to be explored. This results in a huge set of parameters like the choice of algorithms, quantization, suboptimal calculations, or degrees of parallelism. The  exploration of this design space is very computational intense but can easily be parallelized. It is therefore perfectly suited for HPC clusters like Elwetritsch. The  Microelectronic Systems Design Research Group is specialized in this methodology for the domains of communications systems, DRAMs, neural networks, and complex network analysis.